1. Technical Field
This invention relates to a plating process for forming a conducting film by electrolytic plating and a process for manufacturing a semiconductor device by the plating process, as well as a plating apparatus.
2. Related Art
A damascene process is one of processes for forming a Cu multilayer interconnection in an LSI. In a damascene process, a monolayer or multilayer insulating film is formed on an Si wafer with a transistor, and the insulating film is selectively removed to form a trench of an interconnection pattern and a hole called as a via for electrical connection between multilayer interconnection layers. Next, a material containing a high-melting metal called as a barrier metal is deposited by chemical vapor deposition or physical vapor deposition. Then, a Cu film called as a seed is deposited by chemical vapor deposition or physical vapor deposition. Cu is grown on the seed by electrolytic plating using the seed as a cathode to fill the trench and the hole with Cu. Subsequently, the barrier metal, the seed Cu and the plated Cu outside the trench and the hole are removed by chemical mechanical polishing. These steps are repeated to form a Cu multilayer interconnection.
In a damascene process, defective burying must be avoided in a Cu film burying process by Cu electrolytic plating. FIG. 19 is a cross-sectional view showing a configuration of a conventional standard Cu plating apparatus. FIG. 20 illustrates relationship between a time and a current applied between an anode electrode and a cathode electrode in the plating apparatus shown in FIG. 19.
A plating apparatus 200 shown in FIG. 19 has a plating bath 201, a plating solution 203 in the plating bath 201, a Cu anode 205 placed in the plating solution 203, a cathode electrode 207 and a power source (not shown). The cathode electrode 207 is placed the circumference of the wafer 209 with a Cu seed 211. In the plating apparatus 200, the cathode electrode 207 comes in contact with the circumference of the wafer 209 such that the film-formation surface in the wafer 209, specifically a surface on which the Cu seed 211 is to be formed and with being kept horizontal, they are immersed in the plating solution 203 to form a Cu film. During the immersion, the plating solution 203 is supplied to the wafer surface by an upward jet flow.
Since a growth rate in electrolytic plating is proportional to a current, film formation is conducted at a constant current in the light of film-thickness controllability. Since the plating solution 203 dissolves the Cu seed 211, a negative potential is applied between the Cu anode 205 and the cathode electrode 207 before and during immersing the wafer for preventing the Cu seed 211 from being dissolved in the plating solution. As shown in FIG. 20, the system is designed to apply a given current from the moment of liquid contact of the wafer 203.
As a method for controlling a current in horizontal bath immersion, Japanese Patent Application No. 2004-218080 has disclosed that constant-voltage and constant-current control is conducted before and after placing a plating solution. The application has described that defective burying can be thus prevented during plating a copper film over a semiconductor wafer.
However, the wafer 209 is actually immersed into the plating solution 203 with the surface of the plating solution 203 waves. Since the wafer 209 is put into the bath horizontally to the surface of the plating solution 203, the whole surface of the wafer 209 does not come into contact with the plating solution 203 at one time due to a wave as shown in FIG. 21. FIG. 21 is a cross-sectional view illustrating that the wafer 209 is moved down toward the surface of the plating solution 203. In the plating apparatus 200, a given current is applied to a narrow area where the wafer 209 is in contact with the plating solution 203, so that a current density may be considerably increased in a liquid-contacting area as shown in FIG. 22, causing undesired film formation. FIG. 22 shows relationship between a time, a current intensity and a current density in a conventional plating process.
In order to solve the problem, Japanese Patent Application No. 2001-32094 has disclosed that during a period from the initial contact of a surface to be plated with a plating solution to complete contact of the whole surface with the solution, a voltage is kept constant until the complete contact with the solution for preventing variation in a current density due to fluctuation in a liquid-contact area caused by a wave. The reference has described that the technique allows for plating with improved uniformity and appearance when plating a wafer with a metal seed.
However, since the wafer 209 is inserted horizontally to the liquid surface in the plating apparatus 200, bubbles may adhere to the interface between the surface of the wafer 209 and the plating solution 203. FIG. 23 is a cross-sectional view illustrating adhesion of bubbles to the surface of the wafer 209 in contact with the plating solution 203. In FIG. 23, an electric field is intensified in an area without bubbles 213. Once bubbles adhere to the surface of the wafer 209, plating does not proceed in an area with bubbles, which may cause defective burying. Thus, a current control has been actually difficult.
Attempting to solve the problem, Japanese Patent Application No. 2003-129297 has disclosed that a semiconductor wafer is immersed into a plating solution at an predetermined angle to the horizontal direction and in an immersion step, is applied a voltage equal to that applied in a film forming step after the immersion. The reference has described that immersion of the wafer at a given angle can prevent bubbles from being trapped by a hole in the wafer. Herein, immersing a wafer surface to be film-formed into a plating bath at an angle to the surface of a plating solution is called “inclined insertion” as appropriate.